1. Field of the Invention
The present invention relates to an LSI semiconductor device and, more particularly, to a vertical MOS semiconductor device.
2. Description of Related Art
FIG. 6A and FIG. 6B are a sectional view and a top plan view, respectively, of a conventional vertical metal-oxide-semiconductor (MOS) device. FIG. 6A is the sectional view taken at the line C-D of FIG. 6B. FIG. 6B does not show an aluminum wire 24 which will be discussed hereinafter. The vertical MOS semiconductor device is comprised of a cell region 100 wherein a plurality of vertical MOS transistors are formed, and a peripheral region 110 wherein elements for providing a high breakdown voltage characteristic are formed. In a chip of this semiconductor device, the peripheral region 110 is positioned to surround the cell region 100. Referring to FIG. 6A, p-type diffusion regions 12, N.sup.+ source diffusion regions 14, and p-type take-out regions 16 are provided in an N.sup.- epitaxial layer 10 formed on a main surface of an N.sup.+ substrate 9. Provided on the main surface of the N.sup.- epitaxial layer 10 are an insulating film 18, gate oxide films 20, gate electrodes 22, and aluminum wires 24. A gold (Au) electrode 26 is provided on a rear surface of the N.sup.+ substrate 9. Gates, sources, and drains are connected to the poly-silicon electrodes 22, the aluminum wire 24, and the gold electrode 26, respectively.
Referring to FIG. 7, a manufacturing method for the conventional vertical MOS semiconductor device will be described.
As shown in FIG. 7A, on the main surface of the N.sup.- epitaxial layer 10 formed on the N.sup.+ substrate 9, the insulating film 18 is formed in the peripheral region 110 by the local oxidation of silicon. Thereafter, gate oxide films 20 are formed by thermal oxidation on the main surface of the N.sup.- epitaxial layer 10 of the cell region 100. To form the gate electrodes 22, a phosphor-doped poly-silicon film is formed by the low-pressure chemical vapor deposition (CVD) on the gate oxide films 20. This phosphor-doped poly-silicon is subjected to a photolithography process and an etching process to form the predetermined gate electrodes 22. Using the gate electrodes 22 as masks, exposed surfaces of the gate oxide films 20 are etched. Next, a predetermined dosage of a p-type impurity ions are injected into the exposed N.sup.- epitaxial layer 10 at a predetermined acceleration energy in an ion injection process. Then, the p-type diffusion regions 12 are formed in the cell region 100 and the peripheral region 110 by heat treatment. This condition is illustrated in FIG. 7B. To secure the high breakdown voltage characteristic, it is necessary to sufficiently ease a concentration of electric field s at a junction of the p-type diffusion region of the peripheral region 110. For the purpose of securing the high breakdown voltage characteristic, a junction depth Xj of the p-type diffusion regions 12 is set, for example, to 4 to 7 .mu.m.
There are, for example, two other methods for securing the high breakdown voltage characteristic. In one method, the cell region 100 is masked using a resist film, and highly accelerated energy ion injection is performed to form deeper p-type diffusion regions than before in the peripheral area 110. In another method, a guard ring is formed in the peripheral region 110.
Subsequently, as shown in FIG. 7C, the p-type take-out regions 16 composed of the N+ source diffusion regions 14 and the p-type take-out regions 16 composed of a P.sup.+ diffusion layers are formed by an ion injection process and a heat treatment process. An aluminum alloy is deposited on the exposed p-type take-out regions 16, and the aluminum alloy is formed into the aluminum wire 24 of a predetermined pattern by a photolithography and etching process. A metal, namely, gold is deposited on a rear surface of the N.sup.+ substrate 9 to form the gold electrode 26. The state is illustrated in FIG. 7D.
In the vertical MOS semiconductor device described above, the junction depth Xj of the diffusion layer of the p-type diffusion regions 12 of the vertical MOS transistor of the cell region 100 is also 4 .mu.m or more. A channel length L, which is a diffusion length in the horizontal direction of the p-type diffusion region 12 shown in FIG. 7D must be set to a large value, namely, 3 .mu.m or more.
The large channel length L (3 .mu.m or more) makes it impossible to reduce channel resistance. To reduce an on-resistance, a chip of the vertical MOS semiconductor device must be larger to make the cell region 100 layer. For this reason, applying a vertical MOS semiconductor device with lower on-resistance to an output section of another semiconductor device, such as a relay, would result in a larger package of a semiconductor device on which a plurality of the vertical MOS semiconductor devices are mounted. This has been posing a problem in that a semiconductor device equipped with the vertical MOS semiconductor devices cannot be reduced in size and weight. Furthermore, it has been difficult to reduce the junction depth of a diffusion layer of the p-type diffusion regions 12 of the peripheral region 110 because of a required high breakdown voltage characteristic.